The present invention generally relates to a semiconductor memory device, and more specifically, is directed to a method of programming a non-volatile semiconductor memory device capable of cutting off a leakage current flowing through a parasitic MOS transistor formed between adjoining memory cells of the same row, and a leakage current flowing through a string select transistor.
This application relies for priority upon Korean Patent Application No. 2000-083619, filed on Dec. 28, 2000, the contents of which are herein incorporated by reference in their entirety.
There is a need to electrically erase and program semiconductor memory devices without refreshing data stored within the semiconductor memory device. Also, there is a continuing need to increase storage capacity and integration level of the memory devices. A NAND-type flash memory device is one example of non-volatile memory devices that can provide mass storage capacity and a high integration level without refresh of data stored therein. Since such a flash memory is able to retain data even in power-off state, it has widely been used in electric apparatuses (e.g., mobile telephones, portable computers, Personal Digital Assistants, digital cameras, and so forth).
A non-volatile memory device such as a NAND-type flash memory includes electrically erasable and programmable read only memory cells, which are called xe2x80x9cflash EEPROM cellsxe2x80x9d. Conventionally, a flash memory cell includes a cell transistor or a floating gate transistor. The transistor, which is formed at a pocket P-well area as a substrate, includes N-type source and drain regions spaced out a predetermined distance apart from each other, a floating gate located on a channel region between the source and drain regions to store charges, and a control gate located on the floating gate.
Referring now to FIG. 12, an array configuration of a conventional NAND-type flash memory device is illustrated. A memory cell array is formed at a pocket P-well area, and includes a plurality of cell strings 10 each corresponding to bitlines. The pocket P-well area is formed in an N-well area of a P-type semiconductor substrate (see FIG. 2). For simplicity of the drawing, there are shown only two bitlines BL0 and BL1 and two cell strings 10 corresponding thereto. Each of the cell strings 10 is made of a string select transistor (SST) as a first select transistor, a ground select transistor (GST) as a second select transistor, and a plurality of flash EEPROMs (MCm (m=0-15)) serially coupled between the select transistors. SST and GST. The string select transistor SST has a drain coupled to a corresponding bitline, and a gate coupled to a string select line SSL. The ground select transistor GST has a source coupled to a common source line CSL, and a gate coupled to a ground select line GSL. The flash EEPROM cells MC15-MC0 are serially coupled between a source of the string select transistor SSL and a drain of the ground select transistor GSL, and have gates coupled to corresponding wordlines WL15-WL0, respectively.
Initially, flash EEPROM cells of a memory cell array are erased to have a threshold voltage of, for example, xe2x88x923 V. For programming the flash EEPROM cells, a high voltage Vpgm is applied to a selected wordline and a pass voltage Vpass is applied to an unselected wordline. Thus, a threshold voltage of a selected memory cell is boosted, while threshold voltages of the other (unselected) memory cells are not changed.
If it is desired to not program unselected flash EEPROM cells coupled to the selected wordline while programming selected memory cell(s) coupled to the same wordline, problems occur.
When a program voltage is applied to the selected wordline, the program voltage is applied to not only the selected flash EEPROM cell but also unselected flash EEPROM cells arranged along the same wordline. The unselected flash EEPROM cell coupled to the wordline, particularly, a flash EEPROM cell adjacent to the selected cell is programmed. Inadvertent programming of an unselected cell coupled to a selected wordline is called xe2x80x9cprogram disturbxe2x80x9d.
One of technologies for preventing the program disturb is a program inhibit method using a self-boosting scheme, which is disclosed in U.S. Pat. No. 5,677,873 entitled xe2x80x9cMETHOD OF PROGRAMMING FLASH EEPROM INTEGRATED CIRCUIT MEMORY DEVICE TO PREVENT INADVERTENT PROGRAMMING OF NONDESIGNATED NAND MEMORY CELLS THEREINxe2x80x9d, and U.S. Pat. No. 5,991,202 entitled xe2x80x9cMETHOD FOR REDUCING PROGRAM DISTURB DURING SELF-BOOSTING IN A NAND FLASH MEMORYxe2x80x9d.
An operation timing view based upon the foregoing program inhibit method using the self-boosting scheme is illustrated in FIG. 13. A voltage of 0 V is applied to a gate of a ground select transistor GST, cutting off a ground path. A voltage of 0 V is applied to a selected bitline (e.g., BL0), and a power supply voltage VCC of 3.3 V or 5 V is applied to an unselected bitline (e.g., BL1). At the same time, the power supply voltage VCC is applied to a gate of a string select transistor SST coupled to a bitline BL1 (see FIG. 12), charging a source of the string select transistor SST (or a channel of a program inhibit cell transistor) up to VCC-Vth (here, Vth denotes a threshold voltage of the string select transistor SST). The string select transistor SST is substantially shut off. This interval is called xe2x80x9cbitline setup intervalxe2x80x9d.
Then, a program voltage Vpgm is applied to a select wordline and a pass voltage Vpass is applied to unselect wordlines, boosting a channel voltage Vchannel of a program inhibit cell transistor. Fowler-Nordheim (F-N) tunneling is not created between a floating gate and a channel, so that the program inhibit cell transistor retains an initial erase state. This interval is called xe2x80x9cprogram intervalxe2x80x9d. If programming the selected memory cell is completed, a discharge operation is carried out to discharge a potential of a bitline. For the bitline setup, program, and discharge intervals, a pocket PPWELL area and an N-well NWELL are biased with a ground voltage, as shown in FIG. 13.
When the foregoing program inhibit method using the self-boosting scheme is employed on a flash memory device, unfortunately, one problem occurs. The higher the integration level of the flash memory device is, the narrower the spacing between adjoining signal lines is. This causes a signal line coupling through a parasitic capacitance (see FIG. 12) that is created between adjoining signal lines. For example, assume that a memory cell MC15 adjacent to (or located beneath) the string select transistor SST is programmed. When a program voltage is applied to a select wordline WL15 coupled to the memory cell MC15, a voltage (e.g., power supply voltage) of the string select line SSL is boosted higher than a power supply voltage VCC, due to a coupling to a select wordline WL15 through a parasitic capacitance, as shown in FIG. 13. The voltage boosting makes charges in the channel of the program inhibit cell transistor discharged to a bitline through a string select transistor (which is changed from a shut-off state to a turn-on state by the voltage boosting). In other words, the channel voltage Vchannel (or inhibit voltage Vinhibit) of the program inhibit cell transistor is lowered as much as xcex94V (determined by a coupling ratio of a wordline to a string select line and a program voltage) in proportion to the boosting voltage of the string select line SSL, as shown in FIG. 13. Therefore, the program inhibit cell transistor is inadvertently programmed (i.e., program disturb occurs).
Another problem is caused by employing the foregoing program inhibit scheme. That is, xe2x80x9cprogram disturbxe2x80x9d occurs in a program inhibit flash EEPROM cell that is adjacent to a flash EEPROM cell to be programmed by a leakage current flowing through a parasitic MOS transistor. This will now be explained in detail hereinbelow.
With reference to FIG. 14 illustrating a cross-sectional view of an array configuration taken along line a dotted line A-Axe2x80x2 of FIG. 12, flash EEPROM cells coupled to the same wordline WL14 are electrically isolated from each other by field (or field oxide) zones 12 formed in a pocket P-well region. A parasitic MOS transistor is made of adjoining flash EEPROM cells, a wordline WL14, and a pocket P-well as a bulk. A channel region of a program inhibit cell out of the EEPROM cells acts as a drain region of the parasitic MOS transistor. A channel region of a program cell acts as a source region. The wordline WL14 acts as a gate of the parasitic MOS transistor. A pocket P-well region, which is adjacent to the field zone 12 between the source and drain regions, acts as the channel region of the parasitic MOS transistor.
If a program voltage Vpgm applied to the wordline W14 is higher than a threshold voltage of the parasitic MOS transistor, the parasitic MOS transistor is turned on. This makes a leakage current flow from the channel region of the program inhibit cell to the channel region of the program cell through the turned-on MOS transistor. A self-boosted channel voltage of the program inhibit cell is then lowered, so that the program inhibit flash EEPROM cell suffers from xe2x80x9cprogram disturbxe2x80x9d.
A threshold voltage of a parasitic MOS transistor is boosted to solve such a problem. In order to boost a threshold voltage of a parasitic MOS transistor, a method of implanting impurities into a field zone has been suggested. Unfortunately, a breakdown voltage of a drain region is lowered. Furthermore, to increase an impurity concentration is to be restrictive with a trend toward decreasing the size of a memory cell array. Also, a method of directly biasing a pocket P-well area with a negative voltage has been suggested. Unfortunately, it takes a relatively long time to charge the pocket P-well area, thereby increasing the total programming time.
Embodiments of the present invention provide a method of programming a non-volatile semiconductor memory device that can prevent program disturb by boosting threshold voltages of a string select transistor and a parasitic MOS transistor formed between adjoining memory cells of the same row.
According to an aspect of the present invention, a method of programming a non-volatile semiconductor memory device in order to prevent a leakage current from flowing through a string select transistor and a parasitic MOS transistor formed between a program inhibit cell and a program cell is provided. The memory device is made of a semiconductor substrate of a first conductive type (e.g., P-type); a first well area of a second conductive type (e.g., N-type) formed at the semiconductor substrate of the first conductive type; a second well area of the first conductive type formed in the first well area; a memory cell array formed at the second well area, and composed of a plurality of strings each being made of a first select transistor having a drain connected to a corresponding bitline, a second select transistor having a source connected to a common source line, and a plurality of memory cells serially connected between a source of the first select transistor and a drain of the second select transistor; a first select line commonly connected to first select transistors of the strings; a second select line commonly connected to second select transistors of the strings; a plurality of wordlines each being connected to memory cells of the respective strings; and page buffers, each being coupled to bitlines corresponding to the respective strings, for temporarily storing data to be programmed in the memory cell array. In the programming method, either a ground or power supply voltages is applied to each of the bitlines depending upon data bits stored in the page buffers, with the second well area biased with the ground voltage. The ground voltage applied to the second well area is cut off so that the second well area holds a floating state. Under this condition, the second well area is biased with a coupling voltage lower than the ground voltage through either a coupling capacitance between the second well area and the common source line, or a coupling capacitance between the second well area and the first well area. With the floated second well area biased with the coupling voltage, a program voltage is applied to a selected one of the wordlines, and a pass voltage is applied to unselected wordlines.